QEEE Session on DIGITAL SYSTEM DESIGN
6th, 13th & 17th February, 2017
QEEE session on "Digital System Design" was organized by IIT, Madras under D2S (Direct to Student) Program at Dronacharya College of Engineering, Gurgaon through ICT on 6th , 13th and 17th February 2017. The session was conducted by Dr. T G Venkatesh from IIT Bombay . The session was attended by 34 students of ECE Department under the guidance of Faculty Coordinator Mr. Ashish Gambhir, Assistant Professor, ECE.
Digital System Design is an important component in Engineering Educationand is pervasive throughout science and engineering. In this coursethe rudiments of Digital Systems focusingprimarily on their design were discussed.
Day 1: 6th Feb 2017
In the first session Dr. Venkatesh introduced the sequential circuits such as flip-flops and counters. He explained flip-flops are basic building blocks of synchronous i.e sequential circuits. The function of a flip-flops is to synchronize a data input (which is asynchronous, i.e can change at any point of time) with respect to a predictable, synchronous clock. D flip-flops are the ones commonly used to implement synchronous circuits. The excitation tables of flip-flops and the analysis of clocked sequential circuits was also discussed. Next he explained counters are the circuits made using flip-flops connected in a serial, i.e sequential fashion. The Q output pins of all the flip-flops are considered as counter outputs. With each edge of the input clock, the value indicated by Q pins of flip flops gets incremented by 1. Counters can count up / down and some counter ICs have pin settings to halt the counting.
Day 2: 13th Feb 2017
In the second session, he explained Mealy and Moore machines. He told a Mealy Machine is an FSM whose output depends on the present state as well as the present input whereas Moore machine is an FSM whose outputs depend only on the present state. He then took the examples of Digital Systems and explained its designing using the Mealy and Moore machines. He also discussed the Sequential Network Design and equivalent sequential circuits.
Day 3: 17th Feb 2017
In the third session the topics discussed were Memory Decoding, Address Multiplexing, ASM Charts and their realization, asynchronous sequential circuits and state table reduction using an implication table.
The session was informative and appreciated by the students. The student completed their session’s requirements and their quiz and assignments.