Workshop on VLSI SOC Design Verilog HDL

8th March 2024

Fifteen students of 2^nd and 4^th semester from ECE/EEE/ECS Department, Dronacharya College of Engineering, Gurugram attended a workshop on “VLSI SOC Design Verilog HDL” at IIT Delhi.  The workshop was conducted by VLSI FOR ALL Pvt Limited, a leading organization in VLSI technology.

The workshop aimed to familiarize participants with the concepts of VLSI SOC design using Verilog HDL.

The workshop commenced with an introductory session, where participants were introduced to the basics of VLSI design and the significance of SOC design methodologies. Mentors gave insights into the role of Verilog HDL in describing hardware systems at various levels of abstraction.  Mentors also explained designing and implementing complex digital systems on a single chip. The workshop comprised both theoretical sessions and practical hands-on exercises to enhance the participant’s skills in Verilog HDL programming.

The workshop not only enhanced the participants' understanding of Verilog HDL programming but also equipped them with essential skills required in the field of VLSI engineering.